LFD114 - Issue on describing Ztso disallowing store -> load reordering on ch 6, lesson 9

Afsan

Hello!

I was reading chapter 06. "MEMORY MODEL -ARM & RISCV-V" and in Lesson 9, "RISC-V TSO (Ztso): Who Enables It, When, and What Changes", I encountered this line :

"Ztso is the RISC-V extension that makes the machine behave like a Total Store Order (TSO) system (i.e., the same high-level ordering guarantees programmers expect on x86). In effect, ordinary loads act like acquire, ordinary stores act like release, and store→load reordering is disallowed. Given the hardware is already “paying” this cost, when targeting TSO hardware the compilers no longer need to emit fence instructions to implement load-acquire or store-release. "

It says store->load reordering is disallowed for TSO.

I was reading the "Computer Architecture: A Quantative appraoch, 7th edition, page 431", it said:

"Sequential consistency requires maintaining all four possible orderings:

R -> W; R -> R; W -> R; and W -> W.

The relaxed models are defined by the subset of four orderings they relax: Relaxing only the W -> R ordering yields a model known as total store ordering or processor consistency."

So, I am confused as to why it said "store->load reordering is disallowed". The book says its relaxed.