Welcome to the Linux Foundation Forum!

eDP display screen timing issues in kernel

Options

Hey everyone, first I would like to say I'm not very knowledgable in working with the kernel of linux, but I understand it a little. However here's my problem and some of the things I've done to try and solve it.

First I have a rk3399 device that I'm trying to drive a 3840x1100 eDP panel directly from the board. According to the documentation of the panel, it says that the typical clock is 269.5 MHz and the EDID info in the documentation states Horizontal blanking = 160, Sync Offset =48, Sync pulse = 32, Vertical blanking = 48, Sync Offset = 3, sync pulse = 5.
I would assume that means the hBP = 80, hPW=32, hFP = 48, vBP = 40, vPW = 5, and vFP = 3.
Now the modeline I'm getting is Modeline "3840x1100_60.00" 353.18 3840 4088 4504 5168 1100 1101 1104 1139 -HSync +Vsync which is nothing like what the documentation says.

I'm compiling Android 7.1 Industrial build, and I've added
` display-timings {
native-mode = <&timing0>;

                    timing0: timing0 {
                            clock-frequency = <202500000>;
                            hactive = <3840>;
                            vactive = <1100>;
                            hfront-porch = <48>;
                            hsync-len = <32>;
                            hback-porch = <80>;
                            vfront-porch = <3>;
                            vsync-len = <10>;
                            vback-porch = <28>;
                            hsync-active = <0>;
                            vsync-active = <1>;
                            de-active = <0>;
                            pixelclk-active = <0>;
                    };
            };`

to the DTS and I've also added
`static const struct drm_display_mode boe_nv140xtm_n52_mode = {
.clock = 202500,
.hdisplay = 3840,
.hsync_start = 3840 + 80,
.hsync_end = 3840 + 80 + 32,
.htotal = 3840 + 80 + 32 + 48,
.vdisplay = 1100,
.vsync_start = 1100 + 3,
.vsync_end = 1100 + 3 + 10,
.vtotal = 1100 + 3 + 10 + 28,
.vrefresh = 60,
.flags = DRM_MODE_FLAG_NVSYNC// | DRM_MODE_FLAG_NHSYNC,
};

static const struct panel_desc boe_nv140xtm_n52 = {
.modes = &boe_nv140xtm_n52_mode,
.num_modes = 1,
.bpc = 8,
.size = {
.width = 344,
.height = 99,
},
.delay = {
.prepare = 20,
.enable = 20,
.unprepare = 20,
.disable = 20,
},
};`

to kernel/drivers/gpu/drm/panel/panel-simple.c. I've tried many different combinations of the timings and clock with varying degrees of partial success. For example, the info I added above with a 202.5 MHz clock works a little, until I do a few things, like open the app menu, then the screen will start flickering. If I increase the clock to closer to the 269MHz, the screen is completely messed up. It doesn't appear that the screen is sending the correct EDID information, or perhaps the fork I'm using isn't reading EDID properly. That gets a bit past my knowledge.

Can anyone help me get this screen working with this board?

Categories

Upcoming Training