Regarding Store Logic Implementation in one clock cycle

I’m a 4th-year undergraduate student at PES University, currently working on building a custom RISC-V SoC from scratch as part of my capstone project. We've completed the core design and are currently working on integrating the AMBA AHB protocol.

I had a question regarding byte-level store operations in our current design. Right now, to prevent overwriting of unrelated bits during a byte store, we read the full 32-bit word, modify only the target byte using masking and merging logic, and write it back. This ensures correctness, but it takes two clock cycles — one for reading and one for writing.